In general, electroplating can be carried out to form metal layers in integrated circuit (semiconductor) devices. In particular, since an integrated circuit device, such as an Ultra-High Speed Integrated circuit (ULSI), may operate much faster than other devices, copper (Cu) layers having relatively low resistance can be used to suppress the occurrence of ElectroMigration (EM) therein. It is known to use electroplating to form Cu wiring by patterning Cu layers. However, it may be difficult to pattern Cu using general etching methods because the copper may be prone to oxidization in air. Thus, the Cu wiring is generally formed using electroplating in combination with a damascene process.
However, the electroplating and damascene processes may promote voids in the Cu wiring. In detail, voids may occur when a contact hole, through which Cu deposited, or a trench used to form the wiring, is not completely filled or filled irregularly. The voids may result in the malfunction the electrical wiring of an integrated circuit device. Also, an electrolyte solution, which is used in the electroplating process, may remain in the void, thereby deteriorating the performance of a integrated circuit device.
FIG. 1 is a cross-sectional view of a void A occurring in a Cu layer 18. Referring to FIG. 1, the Cu layer 18 is formed by electroplating and a damascene process to form Cu wiring in an integrated circuit device. An insulating layer 11 is formed on a integrated circuit substrate 10. Then, the insulating layer 11 is patterned according to the damascene process to form a hole 12 and a trench 13. An underlying layer, such as the integrated circuit substrate 10 or a lower conductive layer, can be electrically connected through the hole 12. Thus, the hole 12 may be a contact hole or a via that passes through the insulating layer 11. The trench 13 is formed as a line shape so as to pattern the Cu layer 18 as a wire on the insulating layer 11.
Next, a barrier metal layer 14, such as tantalum nitride (TaN), is formed on the resultant structure in which the trench 13 and the hole 12 are formed. Then, a Cu seed layer 16 is formed thereon. Thereafter, a Cu layer 18 is deposited using an electroplating process to fill the hole 12.
During the deposition of the Cu layer 18, it may be difficult to completely fill the hole 12 with the Cu layer 18 due to the high aspect ratio of the hole 12, which may contribute to the formation of the void A during the electroplating process. A reduction in the design rule of integrated circuit device can result in an increase in the aspect ratio of a hole to three or more. In other words, the hole 12 can be three times or more times deeper than it is wide. Thus, it may be more likely that the void A can occur in the hole 12 because the edges of the mouth of the hole 12 are deposited faster than other flat portions, and thus the deposition at the mouth of the hole 12 can rapidly obstruct the opening of the hole 12 before the inner portion of the hole beneath the mouth of the hole 12 is completely filled with the Cu layer 18, thereby reducing the reliability of the integrated circuit device. Moreover, an electrolyte solution used for the electroplating process may be trapped in the void A, thereby further reducing the reliability of the integrated circuit device.